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NX2113/2113A
300kHz & 600kHz SYNCHRONOUS PWM CONTROLLER WITH PROGRAMMABLE BUS UVLO
PRELIMINARY DATA SHEET Pb Free Product
DESCRIPTION
Synchronous Controller in 10 Pin Package The NX2113 controller IC is a synchronous Buck conBus voltage operation from 2V to 25V troller IC designed for step down DC to DC converter Enable pin allows programmable BUS UVLO applications. Synchronous control operation replaces the Less than 50 nS adaptive deadband traditional catch diode with an Nch MOSFET resulting Internal 300kHz for 2113 and 600kHz for 2113A in improved converter efficiency. The NX2113 controller Internal Digital Soft Start Function is optimized to convert bus voltages from 2V to 25V to Separated power ground and analog ground for outputs as low as 0.8V voltage using Enable pin to extra noise filtering program the BUS voltage start up threshold. The NX2113 n Pb-free and RoHS compliant operates at 300kHz while 2113A is set at 600kHz operation which together with less than 50 nS of dead band provides an efficient and cost effective solution. n Graphic Card on board converters Other features of the device are: n Memory Vcore or Vddq supply Internal digital soft start; Vcc undervoltage lock out; n On board DC to DC such as Output undervoltage protection with digital filter and shut12V, 5V to 3.3V, 2.5V or 1.8V down capability via the enable pin. n Hard Disk Drive
L2 1uH C3 47uF R3 10 R5 68k C4 1uF
7
n n n n n n n
FEATURES
APPLICATIONS
TYPICAL APPLICATION
Vin +12V
C5 1uF C6 1uF Cin 270uF,18mohm
Vin +5V
D1
6
5
1 2
Vcc PVcc BST
C7 0.1uF M1 L1 1.5uH
OFF ON
R8 10k 2N3904 R7 10k
C9 1uF
R6 12.4k C1 47pF C2 2.7nF R4 11k
NX2113A
EN Comp
Hdrv SW Ldrv
9
10
8
Fb PGnd Gnd
3 11
4
M2
Co 3x (220uF,12mohm)
Vout +1.6V,10A
R2 10k 1%
R1 10k 1% R9 1.2k C8 2.2nF
Figure1 - Typical application of 2113A
ORDERING INFORMATION
Device NX2113CMTR NX2113CUTR NX2113ACMTR NX2113ACUTR
Rev. 2.0 11/18/05
Temperature 0 to 70oC 0 to 70o C 0 to 70oC 0 to 70o C
Package MLPD-10L MSOP-10L MLPD-10L MSOP-10L
Frequency 300kHz 300kHz 600kHz 600kHz
Pb-Free Yes Yes Yes Yes 1
NX2113/2113A
ABSOLUTE MAXIMUM RATINGS
Vcc to GND & BST to SW voltage ................... 6.5V BST to GND Voltage ...................................... 35V Storage Temperature Range ............................. -65oC to 150oC Operating Junction Temperature Range ............. -40oC to 125oC CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
10-LEAD PLASTIC MSOP
JA 200o C/W
BST 1 HDrv 2 PGnd/Gnd 3 LDrv 4 PVcc 5 10 SW 9 Comp 8 Fb 7 EN 6 Vcc
BST 1 HDrv 2 PGnd 3 LDrv 4 PVcc 5 PAD (Gnd)
10-LEAD PLASTIC MLPD
JA 52o C /W
10 SW 9 Comp 8 Fb 7 EN 6 Vcc
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc = 5V, and TA = 0 to 70oC. Typical values refer to TA = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
PARAMETER Reference Voltage Ref Voltage Ref Voltage line regulation Supply Voltage(Vcc) VCC Voltage Range VCC Supply Current (Static) VCC Supply Current (Dynamic) Supply Voltage(VBST) VBST Supply Current (Static) VBST Supply Current (Dynamic) Under Voltage Lockout VCC-Threshold VCC-Hysteresis SS Soft Start time SYM VREF Test Condition 4.5VVCC ICC (Static) Outputs not switching ICC CLOAD=3300pF FS=300kHz (Dynamic) IBST (Static) Outputs not switching IBST CLOAD=3300pF (Dynamic) VCC_UVLO VCC Rising VCC_Hyst VCC Falling Tss Fsw=300Khz, 2113 Fsw=600Khz, 2113A FS=300kHz
0.15 5
mA mA
4.1 0.22 3.4 1.7
V V mS
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PARAMETER Oscillator (Rt) Frequency Ramp-Amplitude Voltage Max Duty Cycle Min Duty Cycle Error Amplifiers Transconductance Input Bias Current FB Under Voltage Protection FB Under voltage threshold EN Enable Threshold Voltage Enable Hysterises High Side Driver(CL=3300pF) Output Impedance , Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time Low Side Driver (CL=3300pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current Rise Time Fall Time Deadband Time Rsource(Ldrv) Rsink(Ldrv) I=200mA I=200mA 1.1 0.5 50 50 30 ohm ohm ns ns ns SYM FS VRAMP Test Condition 2113 2113A Min TYP 300 600 2.1 93 0 2100 10 0.4 Enable ramp up 1.25 0.2 MAX Units kHz kHz V % % umho nA V V V
Ib
Rsource(Hdrv) Rsink(Hdrv) THdrv(Rise) THdrv(Fall) Tdead(L to H)
I=200mA I=200mA VBST-VSW =4.5V VBST-VSW =4.5V Ldrv going Low to Hdrv going High, 10%-10%
1.1 0.8 50 50 30
ohm ohm ns ns ns
TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv L) going High, 10% to 10%
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PIN DESCRIPTIONS
PIN # 1 PIN SYMBOL BST PIN DESCRIPTION This pin supplies voltage to the high side driver. A high frequency ceramic capacitor of 0.1 to 1 uF must be connected from this pin to SW pin. High side MOSFET gate driver. Power and analog ground pin. For MLPD package, analog ground and power ground are separated, additional pad pin(11) is available for analog ground. Low side MOSFET gate driver. Ldrv supply voltage. A 1uF high frequency cap must be connected from this pin to GND directly. 6 Vcc Voltage supply for the internal circuit as well as the low side MOSFET gate driver. A 1uF high frequency ceramic capacitor must be connected from this pin to GND pin. Pull up this pin to Vcc for normal operation. Pulling this pin down below 1.25V 7 EN shuts down the controller and resets the soft start. This pin can also be used as a UVLO detector for the bus voltage via a resistor divider. This pin is the error amplifier inverting input. This pin is also connected to the output UVLO comparator. When this pin falls below 0.4V, both HDRV and LDRV outputs are latched off. This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop. This pin is connected to the source of the high side MOSFET and provides return path for the high side driver.
2 3
HDRV PGND/Gnd
4 5
LDRV PVcc
8
FB
9
COMP
10
SW
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BLOCK DIAGRAM
VCC
Bias Generator
1.25V 0.8V UVLO POR BST START
EN 1.25/1.15 FB 0.4 START Digital start Up OSC DRVL S R FB Q PVCC DRVH
SW
COMP START GND
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NX2113/2113A
Demo Board Schematic
JP2 1 2 BUS D O 1608C -102 C 12 47u JP3 1 2 VCC C 13 47u R 12 68k C 24 1u C 14 1u Q1 IR F R 3706 VCC2 4 8 7 6 5 R 10 OP 16S P 270M C7 C8 OP L2 BUS1
R4 10
D1 D 1N 5819
VCC1
C9 1u
C 25 1uF
R 11 12.4k
U1 7 6 5 1 C 20 .1u 2 10 Ldrv Hdrv R1 0
EN
VCC
PVCC
BST
9 2N 3904 TP1 R 13 10k Q3 C 16 open R6 open C 17 open C 11 47p R5 11k C 15 2.7n
H d rv COMP
1 2 3
L1 OUT1 D O 5010P-781H C OUT2 1 2
JP 5
N X 2113A
SW
L d rv 4
R 14 10k
R2 0 Fb GND 8 PG N D 3
C1 OP 8 7 6 5
0
C 18 4 Q2 IR F R 3706 1 2 3 2R 5T P E 220M C D2 D 1N 5819 R3 OP
C 21 2R 5T P E 220M C
C 22 2R 5T P E 220M C
R 15 2k
(G N D PAD)
11
GND C 19 2.2n R7 1.2k C2 .1u R8 R9 10k 10k 5 2 3 4 J1 1
Figure 2 - Demoboard design on NX2113A
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Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Quantity 6 2 1 3 1 2 1 3 3 1 1 2 3 2 1 1 2 1 2 1 1 2 1 1 1 1 1 Reference C1,R3,C8,R10,C23,D2 C2,C20 C7 C9,C14,C24 C11 C12,C13 C15 R6,C16,C17 C18,C21,C22 C19 C25 D1 JP2,JP3,JP5 J1 L1 L2 Q1,Q2 Q3 R1,R2 R4 R5 R8,R9,R13,R14 R7 R11 R12 R15 U1 Part OPEN .1uF 16SP270M 1uF 47pF 47uF 2.7nF OPEN 220uF 2R5TPE220MC 2.2nF 1uF D1N5819 CON2 SCOPE TP DO5010P-781HC DO1608C-102 IRFR3706 2N3904 0 10 11k 10k 1.2k 12.4k 68k 2k NX2113 Manufacture
SANYO
SANYO
Tektronics Coilcraft Coilcraft International Rectifier
NEXSEM INC.
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NX2113/2113A
DEMO BOARD WAVEFORM
Figure 3: Output efficiency
Figure 4: Voltage ripple @1.6 V output voltage. (Ch2-ripple, Ch3-Hdrv)
Figure 5: Output voltage transient response for load curent 0A-9A
Figure 6: Start up time(Ch1-input volatge, Ch2-output voltage)
Figure 7: ENABLE function.(Ch1-enable, Ch2-Ldrv, Ch3-output voltage)
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Figure 8: Startup operation waveform
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APPLICATION INFORMATION
Symbol Used In Application Information:
VIN VOUT IOUT FS - Input voltage - Output voltage - Output current - Working frequency
IRIPPLE = =
VIN -VOUT VOUT 1 x x L OUT VIN FS
...(2) 12V-1.6V 1.6v 1 x x = 3A 0.78uH 12v 600kHz
Output Capacitor Selection
Output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load condition is determined by equation(3).
DVRIPPLE - Output voltage ripple DIRIPPLE - Inductor current ripple
Design Example
The following is typical application for NX2113A, the schematic is figure 2. VIN = 12V VOUT=1.6V IOUT=10A DVRIPPLE <=20mV DVDROOP<=80mV @ 10A step FS=600kHz
VRIPPLE = ESR x IRIPPLE +
IRIPPLE 8 x FS x COUT ...(3)
Where ESR is the output capacitors' equivalent series resistance,COUT is the value of output capacitors. Typically when large value capacitors are selected such as Aluminum Electrolytic,POSCAP and OSCON types are used, the amount of the output voltage ripple is dominated by the first term in equation(3) and the second term can be neglected. For this example, POSCAP are chosen as output capacitors, the ESR and inductor current typically determines the output voltage ripple.
Output Inductor Selection
The selection of inductor value is based on inductor ripple current, power rating, switching frequency and efficiency. Larger inductor value normally means smaller ripple current. However if the inductance is chosen too large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:
ESR desire =
VRIPPLE 20mV = = 6.7m IRIPPLE 3A
...(4)
If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 20mV output ripple, POSCAP 2R5TPE220MC with 12m are chosen.
V -V V 1 L OUT = IN OUT x OUT x IRIPPLE VIN FS IRIPPLE =k x IOUTPUT
where k is between 0.2 to 0.4. Select k=0.3, then
LOUT = 12V-1.6V 1.6V 1 x x 0.3 x 10A 12V 600kHz LOUT =0.8uH
...(1)
N=
E S R E x IR I P P L E VR IPPLE
...(5)
Number of Capacitor is calculated as
N= 12m x 3A 20m V
N =1.8 The number of capacitor has to be round up to a integer. Choose N =2. If ceramic capacitors are chosen as output ca9
Choose inductor from COILCRAFT DO5010P781HC with L=0.78uH is a good choice. Current Ripple is recalculated as
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pacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors . For example, one 100uF, X5R ceramic capacitor with 2m ESR is used. The amount of output ripple is of output capacitor. For low frequency capacitor such as electrolytic capacitor, the product of ESR and capacitance is high and L L crit is true. In that case, the transient spec is dependent on the ESR of capacitor. In most cases, the output capacitors are multiple capacitors in parallel. The number of capacitors can be calculated by the following
N= ESR E x Istep Vtran + VOUT x 2 2 x L x C E x Vtran
VRIPPLE
3A = 2m x 3A + 8 x 600kHz x 100uF = 6mV + 6.2mV = 12.2mV
...(9)
where
Although this meets DC ripple spec, however it needs to be studied for transient requirement. Based On Transient Requirement Typically, the output voltage droop during transient is specified as:
0 if L L crit = L x Istep - ESR E x CE V OUT
if
L L crit
...(10)
For example, assume voltage droop during transient is 100mV for 10A load step. If the POSCAP 2R5TPE220MC(220uF, 12m ) is used, the critical inductance is given as:
VDROOP ...(6)
L crit =
ESR E x C E x VOUT = Istep
12m x 220F x 1.6V = 0.42H 10A
The selected inductor is 0.78uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance. number of capacitors is
where is the a function of capacitor, etc.
= =
L x Istep VOUT
- ESR E x CE
0 if L L crit = L x Istep - ESR x COUT V OUT
where
L crit
0.78H x10A - 12mx 220F = 2.24us 1.6V
ESR E x Istep Vtran + VOUT x 2 2 x L x CE x Vtran
if
L L crit
...(7)
N=
...(8)
ESR x COUT x VOUT ESR E x C E x VOUT = = Istep I step
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected output inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the ESR
12m x10A + 80mV 1.6V x (2.24us) 2 2 x1.5H x 220F x 80mV 1.7 =
The number of capacitors has to satisfy both ripple and transient requirement. Overall, we can choose N=3.
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It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters.
FZ1 = FZ2 = FP1 = FP2 =
1 2 x x R 4 x C2 1 2 x x (R 2 + R3 ) x C3 1 2 x x R3 x C3 1 2 x x R4 x C1 x C2 C1 + C2
...(11) ...(12) ...(13) ...(14)
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
Compensator Design
Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, the Bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crossing 0dB with 20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should be chosen.
the compensator. Their locations are shown in figure 10. The transfer function of type III compensator for transconductance amplifier is given by:
Ve 1 - gm x Z f = VOUT 1 + gm x Zin + Z in / R1
For the voltage amplifier, the transfer function of compensator is
Ve -Z f = VOUT Zin
To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R4>>2/gm. R1||R2||R3>>1/gm is desirable.
Zin
Vout
Zf C1 C2 Fb gm Ve R4
A. Type III compensator design
For low ESR output capacitors, typically such as Sanyo oscap and poscap, the frequency of ESR zero caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The following figures and equations show how to realize the type III compensator by transconductance amplifier.
R3 R2 C3 R1
Vref
Figure 9 - Type III compensator using transconductance amplifier
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smaller than 1/10~ 1/5 of the switching frequency. Set FO=45kHz.
Gain(db)
power stage
C3 =
FLC
40dB/decade
1 11 x( ) 2 x x R2 Fz2 Fp1
1 1 1 x( ) 2 x x 10k 7kHz 60kHz =2nF =
R4 = VOSC 2 x x FO x L x x Cout Vin C3
loop gain
FESR
20dB/decade compensator
2V 2 x x 45kHz x 0.78uH x x 660uF 12V 2.2nF =11k =
Choose C3=2.2nF, R 4=11k. 5. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11).
C2 =
FZ1 FZ2
FO FP1
FP2
1 2 x x FZ1 x R 4
Figure 10 - Bode plot of Type III compensator Design example for type III compensator are in order. Use the same power stage requirement as demo board. The crossover frequency has to be selected as FLC1 2 x x 0.75 x 7kHz x 11k = 2.75nF Choose C2=2.7nF. 6. Calculate C 1 by equation (14) with pole F p2 at half the swithing frequency. =
C1 = =
1 2 x x R 4 x FP2
1 2 x x 11k x 300kHz = 48pF
Choose C1=47pF. 7. Calculate R 3 by equation (13).
FLC = =
1 2 x x LOUT x COUT 1
2 x x 0.78uH x 660uF = 7kHz
R3 = =
1 2 x x FP1 x C3
FESR
1 = 2 x x ESR x C OUT 1 2 x x 4m x 660uF = 60kHz =
1 2 x x 60kHz x 2.2nF = 1.2k
Choose R3=1.2k.
2.Set R2 equal to10k, then R1= 10k. 3. Set zero FZ2 = FLC and Fp1 =FESR . 4. Calculate R4 and C3 with the crossover frequency
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B. Type II compensator design
If the electrolytic capacitors are chosen as power stage output capacitors, usually the Type II compensator can be used to compensate the system. noise. The following equations show the compensator pole zero location and constant gain.
Gain=gm x Fz =
R1 x R3 R1+R2
... (15) ... (16) ... (17)
Vout R2 Fb gm R1 Vref Ve R3 C2 C1
1 2 x x R3 x C1 1 2 x x R3 x C2
Fp
For this type of compensator, FO has to satisfy FLCFigure 11 - Type II compensator with transconductance amplifier
FLC = =
1 2 x x L OUT x COUT 1
power stage Gain(db) 40dB/decade loop gain 20dB/decade
2 x x 4.7uH x 1360uF = 2.0kHz
FESR = =
1 2 x x ESR x C OUT
1 2 x x 18m x 1360uF = 6.5kHz
2.Set R2 equal to10k. Using equation 18.
compensator Gain
R1 =
10k x 0.8V = 4.7k 2.5V-0.8V
3. Set crossover frequency at 1/10~ 1/5 of the swithing frequency, here FO=30kHz. 4.Calculate R3 value by the following equation.
FZ FLC FESR FO FP
Figure 12 - Bode plot of Type II compensator Type II compensator can be realized by simple RC circuit without feedback as shown in figure 11. R3 and C1 introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching
R3 = =
VOSC 2 x x FO x L 1 R1+R2 x x x Vin RESR gm R1
2V 2 x x 30kHz x 4.7uH 1 x x 12V 18m 2.5mA/V 10k+4.7k x 4.7k =10.3k
Choose R 3 =10k. 13
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5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole.
C1 = = 1 2 x x R 3 x Fz
In general, the minimum output load impedance including the resistor divider should be less than 5k to prevent overcharge the output voltage by leakage current (e.g. Error Amplifier feedback pin bias current). A minimum load for 5k less (<1/16w for most of application) is recommended to put at the output. For example, in this application, Vout=1.6V The power loss is 1/16W less
1 2 x x 10k x 0.75 x 6.5kHz =10.7nF
Choose C1=10nF. 6. Calculate C2 by setting compensator pole Fp at half the swithing frequency.
C2= = 1 x R 3 x Fs
RLOAD = 1.6V x 1.6V /(1/16W) = 40
Select minimum load is 1k should be good enough.
1 x 10k x 300kH z =106pF
Input Capacitor Selection
Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high frequency noise. The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors can be calculated as:
Choose C2=100pF.
Output Voltage Calculation
Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at 0.8V. The divider consists of two ratioed resistors so that the output voltage applied at the Fb pin is 0.8V when the output voltage is at the desired value. The following equation and picture show the relationship between
IRMS = IOUT x D x 1- D D= VOUT VIN
...(19)
VOUT , VREF and voltage divider. .
R 2 x VR E F V O U T -V R E F
...(18)
VIN = 12V, VOUT=1.6V, IOUT=10A, using equation (19), the result of input RMS current is 3.4A. For higher efficiency, low ESR capacitors are recommended. One Sanyo OSCON SP series 16SP270M 16V 270uF with 4.4A is chosen as input bulk capacitor.
R 1=
wher R2 is part of the compensator, and the e
value of R1 value can be set by voltage divider. Choose R2=10k, to set the output voltage at 1.6V, the result of R1 is 10k.
Vout R2 Fb R1 Vref Voltage divider
Power MOSFETs Selection
The NX2113 requires two N-Channel power MOSFETs. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, maximum current rating, MOSFET on resistance and power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall converter efficiency. In this design example, two IRFR3706 are used. They have the following parameters: V DS=30V, ID =75A,RDSON =9m,QGATE =23nC.
Figure 13 - Voltage divider load
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There are three factors causing the MOSFET power loss: conduction loss, switching loss and gate driver loss. Gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits. It is proportional to frequency and is defined as:
Pgate = (QHGATE x VHGS + QLGATE x VLGS ) x FS
ON R2 1.25/1.15 POR OFF R1 EN Digital start up Vbus
+
...(20)
10k
where QHGATE is the high side MOSFETs gate charge,QLGATE is the low side MOSFETs gate charge,VHGS is the high side gate source voltage, and VLGS is the low side gate source voltage. According to equation (20), PGATE =0.14W. This power dissipation should not exceed maximum power dissipation of the driver device. Conduction loss is simply defined as: Figure 14 - Enable and Shut down NX2113 by pulling down EN pin. The start up of NX2113/2113A can be programmed through resistor divider at Enable pin. For example, if the input bus voltage is 12V and we want NX2113 starts when Vbus is above 8V. We can select ...(21) R2=1.24k
R1 = (8V - 1.25V) x R 2 = 6.8k 1.25V
PHCON =IOUT 2 x D x RDS(ON) x K PLCON =IOUT 2 x (1 - D) x RDS(ON) x K PTOTAL =PHCON + PLCON
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature dependency. As a result, RDS(ON) should be selected for the worst case, in which K equals to 1.4 at 125oC according to IRFR3706 datasheet. Using equation (21), the result of PTOTAL is 0.54W. Conduction loss should not exceed package rating or overall system thermal budget. Switching loss is mainly caused by crossover conduction at the switching transition. The total switching loss can be approximated. tors.
The NX2113 can be turned off by pulling down the ENable pin by extra signal MOSFET or NPN transistor such as 2N3904 as shown in the above Figure. When Enable pin is below 1.15V, the digital soft start is reset to zero. In addition, all the high side is off and output voltage is turned off. A resistor should be added as preload to prevent leakage current from FB pin charging the output capaci-
1 x VIN x IOUT x TSW x FS ...(22) 2 where IOUT is output current, TSW is the sum of TR and TF which can be found in mosfet datasheet, and FS is switching frequency. The result of PSW is 3W. Swithing loss PSW is frequency dependent. PSW =
Feedback Under Voltage Shut Down
NX2113 relies on the Feedback Under Voltage Lock Out (FB UVLO ) to provide short circuit protection. Basically, NX2113 has a comparator compares the feedback voltage with the FB UVLO threshold 0.4V. During the normal operation, if the output is short, the feedback voltage will be lower than 0.4V and comparator will change the state. After certain internal delay, both high side and low side driver will be turned off. The output will be latched. The normal operation should be achieved by removing the short and recycle the VCC. During the start up, the output voltage is discharged to zero by the synchronous FET. FB voltage starts increase from zero when digital start block 15
Soft Start, Enable and shut Down
The NX2113 has a digital start up. It is based on digital counter with 1024 cycles. For NX2113 with 300kHz operation, the start up time is about 3.5ms. For NX2113A with 600kHz operation, the start up time is about half of NX2113, 1.75mS.
Rev. 2.0 11/18/05
NX2113/2113A
operates. Before half of the start up time, the Feedback Under Voltage Lock Out comparator is disabled. After half of start up time, the Feedback UVLO comparator is enabled. The FB UVLO threshold is set to be half of voltage at the positive input of error amplifier. With this set up, if the output is short before soft start, the Feedback UVLO comparator can catch it and turn off the driver. The short circuit operation waveform during normal operation and during the soft start are shown as follows. The Feedback UVLO can provide certain short circuit protection. However, since feedback does not have accurate information of current, this protection only provides certain level of over current protection. MOSFET should design such that it can survive with high pulse current for a short period of time. The value of the capacitor on enable pin to ground and the resistor value of voltage divider on enable pin should be big enough to keep enable pin high during short. Otherwise, once output shorts, the input bus voltage drops, the chip is disabled before Feedback UVLO takes effect, and the system goes into hiccup status. This phenomena is easy to be found during system startup, if related resistor and capacitor value is not big
CH3-FB voltage 0.5V/DIV
enough.
CH1-SW voltage 10V/DIV
CH4-load current 10A/DIV
CH2-Output voltage 1V/DIV
Figure 15 - Operation waveforms during short condition.
CH4-load current 10A/DIV
Figure 17 -Hiccup with start up at short.
CH2-output voltage 1V/DIV
Layout Considerations
The layout is very important when designing high frequency switching converters. Layout will affect noise
CH4-load current 10A/DIV
pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the connection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to
Figure 16 - Feedback UVLO with start up at short.
reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to
Rev. 2.0 11/18/05
16
NX2113/2113A
reduce the ESR replace the single input capacitor with two parallel units. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. In multilayer PCB use one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point.
Rev. 2.0 11/18/05
17
NX2113/2113A
TYPICAL APPLICATION
Dual power supply (+5V BIAS,+12V BUS)
Vin +12V
C4 47uF R5 10 C5 1uF
7
L2 1uH C5 1uF C6 1uF Cin 39uF,31mohm
Vin +5V
R5 1k
D1
6
5
1 2
Vcc PVcc BST
C7 0.1uF M1 L1 4.7uH
R6 1k C1 100pF C2 10nF R4 10k
NX2113
EN Comp
Hdrv SW
9
10
8
Ldrv Fb PGnd/Gnd
3
4
M2
Co 2 x (680uF,36mohm)
Vout +2.5V,4A
R2 4.7k 1%
R1 10k 1%
Figure 18 -Application of NX2113 for 5V bias and 12V input bus
Single power supply (+11V to +24V BUS)
Vin +11~25V
C4 47uF R5 3k R8 76.8k
C6 1uF D1
L2 1uH C5 1uF Cin 2 x (47uF,60mohm)
2N3904 R6 12.7k TL431 R7 10k
7
R9 10k
R5 10
C8 1uF
6
5
1 2
Vcc PVcc BST
C7 0.1uF M1 L1 4.7uH
NX2113
EN Comp Fb
Hdrv SW Ldrv
9
10
C2 10nF C1 100pF R4 10k
8
4
M2
Co 2 x (680uF,36mohm)
Vout +1.6V,5A
PGnd Gnd
3 11
R2 4.7k 1%
R1 10k 1%
Figure 19 -Application of NX2113 for high input bus application
Rev. 2.0 11/18/05
18
NX2113/2113A
TYPICAL APPLICATION
Single Supply 5V Input
Vin +5V
C4 10uF X7R
L2 1uH
R5 10 C8 1uF 7 6
C6 1uF 5 1
D1 C5 1uF C7 0.1uF 2 M1 L1 3.3uH Cin 3 x 22uF X7R
Vcc PVcc BST
NX2113A
EN Comp Fb
3
Hdrv SW Ldrv
9 R4 120k C2 330pF C1 4.7pF
10 Co 10 x 22uF X7R
Vout +1.2V,4A
8
4
M2
PGnd Gnd
11
R2 20k 1%
R1 10k 1% R3 787 C3 820pF
Figure 20 - Application of NX2113 A for 5V input and 1.6V output with ceramic output capacitors
Rev. 2.0 11/18/05
19

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